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Integrated Circuit Systems, Inc.
ICS9248-135
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM& K6
Recommended Application: Motherboard Single chip clock solution for SIS540, SIS630 Pentium II/III and K6 chipsets. Output Features: * 3- CPUs @ 2.5/3.3V, up to 166MHz. * 10 - SDRAM @ 3.3V, up to 166MHz including 2 SDRAM_F's * 7- PCI @3.3V, * 1- 48MHz, @3.3V fixed. * 1- 24/48MHz, @3.3V selectable by I2C (Default is 24MHz). * 2- REF @3.3V, 14.318MHz. Features: * Up to 166MHz frequency support * Support FS0-FS3 trapping status bit for I2C read back. * Support power management: CPU, PCI, SDRAM stop and Power down Mode form I2C programming. * Spread spectrum for EMI control (0 to -0.5%, 0.25%). * FS0, FS1, FS3 must have a internal 120K pull-Down to GND. * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: < 175ps * SDRAM - SDRAM < 250ps * PCI - PCI: < 500ps * CPU - SDRAM: < 500ps * CPU (early) - PCI: 1-4ns (typ. 2ns)
Pin Configuration
VDDREF 1 * REF0/FS3 GNDREF X1 X2 VDDPCI *PCICLK_F/FS1 *PCICLK1/FS2 PCICLK2 GNDPCI PCICLK3 PCICLK4 PCICLK5 PCICLK6 VDD GND SDRAM_STOP# **PD# VDD CPU_STOP# PCI_STOP# GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1 VDDLCPU CPUCLK_F CPUCLK1 GNDL CPUCLK2 VDD SDRAM_F1 SDRAM_F0 GND SDRAM7 SDRAM6 VDD SDRAM5 SDRAM4 GND SDRAM3 SDRAM2 VDD SDRAM1 SDRAM0 VDD 1 48MHz/FS0* 24_48MHz/CPU2.5_3.3#*
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND. ** These inputs have a 120K pullup to VDD. 1 These are double strength.
Functionality Block Diagram
FS3
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz
ICS9248-135
CPU (MHz) 66.6 100.0 150.0 133.3 66.8 100.0 100.0 133.3 66.8 97.0 70.0 95.0 95.0 112.0 97.0 96.2
FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
2
REF[1:0]
CPU DIVDER
Stop
2
CPUCLK [2:1] CPUCLK_F
SDRAM DIVDER
Stop
8
SDRAM [7:0] SDRAM_F [1:0]
CPU2.5_3.3# SDATA SCLK FS[3:0] PD# PCI_STOP# CPU_STOP# SDRAM_STOP# Config. Reg. Control Logic
PCI DIVDER Stop
6 2
PCICLK [6:1] PCICLK_F
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
SDRAM (MHz) 100.0 100.0 100.0 100.0 133.6 133.3 150.0 133.3 66.8 97.0 105.0 95.0 126.7 112.0 129.3 96.2
PCICLK (MHz) 33.3 33.3 37.5 33.3 33.4 33.3 37.5 33.3 33.4 32.3 35.0 31.7 31.7 37.3 32.2 32.1
9248-135 Rev A 1/16/01 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-135
General Description
The ICS9248-135 is the single chip clock solution for Desktop/Notebook designs using the SIS 540/630 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-135 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER 1, 6, 15, 19, 27, 30, 36, 42 2 3, 10, 16, 22, 33, 39, 44 4 5 7 8 14, 13, 12, 11, 9 17 18 20 21 38, 37, 35, 34, 32, 31, 29, 28 23 24 25 26 41, 40 45, 43 46 47 48 PIN NAME VDD REF0 FS3 GND X1 X2 FS1 PCICLK_F FS2 PCICLK1 PCICLK (6:2) SDRAM_STOP# PD# CPU_STOP# PCI_STOP# SDRAM (7:0) SDATA SCLK CPU2.5_3.3# 24_48MHz FS0 48MHz SDRAM_F (1:0) CPUCLK (1:2) CPUCLK_F VDDLCPU REF1 TYPE PWR OUT IN PWR IN OUT IN OUT IN OUT OUT IN IN IN IN OUT IN IN IN OUT IN OUT OUT OUT OUT PWR OUT DESCRIPTION 3.3V Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48MHz output 14.318 MHz reference clock. Frequency select pin. Ground pin for 3V outputs. Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Frequency select pin. Free running PCICLK clock output. Not affected by PCI_STOP# Frequency select pin. PCI clock outputs. PCI clock outputs. Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when input low Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Stops all CPUCLKs clocks at logic 0 level, when input low Stops all PCICLKs clocks at logic 0 level, when input low SDRAM clock outputs Data input for I2C serial input, 5V tolerant input Clock input of I2C input, 5V tolerant input Voltage select 2.5V when high - 3.3V when low Clock output for super I/O/USB default is 24MHz Frequency select pin. 48MHz output clock Free running SDRAM clock outputs. Not affected by SDRAM_STOP# CPU clock outputs. Free running CPUCLK clock output. Not affected by CPU_STOP# Power pin for the CPUCLKs. 2.5V 14.318 MHz reference clock.
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ICS9248-135
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9248-135
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Description Bit7 Bit2 Bit6 Bit5 Bit4 CPU SDRAM 0 0 0 0 0 66.6 100.0 0 0 0 0 1 100.0 100.0 0 0 0 1 0 150.0 100.0 0 0 0 1 1 133.3 100.0 0 0 1 0 0 66.8 133.6 0 0 1 0 1 100.0 133.3 0 0 1 1 0 100.0 150.0 0 0 1 1 1 133.3 133.3 0 1 0 0 0 66.8 66.8 0 1 0 0 1 97.0 97.0 0 1 0 1 0 70.0 105.0 0 1 0 1 1 95.0 95.0 0 1 1 0 0 95.0 126.7 0 1 1 0 1 112.0 112.0 0 1 1 1 0 97.0 129.3 0 1 1 1 1 96.2 96.2 Bit 7, 2, Bit 6:4 1 0 0 0 0 66.8 100.2 1 0 0 0 1 100.2 100.2 1 0 0 1 0 166.0 110.7 1 0 0 1 1 100.2 133.6 1 0 1 0 0 75.0 100.0 1 0 1 0 1 83.3 125.0 1 0 1 1 0 105.0 140.0 1 0 1 1 1 133.6 133.6 1 1 0 0 0 110.3 147.0 1 1 0 0 1 115.0 153.3 1 1 0 1 0 120.0 120.0 1 1 0 1 1 138.0 138.0 1 1 1 0 0 140.0 140.0 1 1 1 0 1 145.0 145.0 1 1 1 1 0 147.5 147.5 1 1 1 1 1 160.0 160.0 0 - Frequency is selected by hardware select, Latched Inputs Bit 3 1 - Frequency is selected by Bit 7, 2, 6:4 0 - Normal Bit 1 1 - Spread Spectrum Enabled 0 - Running Bit 0 1- Tristate all outputs Bit PWD PCI 33.3 33.3 37.5 33.3 33.4 33.3 37.5 33.3 33.4 32.3 35.0 31.7 31.7 37.3 32.3 32.1 33.4 33.4 27.7 33.4 37.5 31.3 35.0 33.4 36.8 38.3 30.0 34.5 35.0 36.3 36.9 26.7 SS 0 to-0.5% 0 to-0.5% 0.25% 0 to-0.5% 0 to-0.5% 0 to-0.5% 0.25% 0 to-0.5% 0.25% 0 to-0.5% 0.25% 0.25% 0.25% 0.25% 0 to-0.5% 0 to-0.5% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25%
00010 Note1
0 1 0
Note: PWD = Power-Up Default Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. The I2C readback for Bits 7, 2, 6:4 indicate the revision code. I2C is a trademark of Philips Corporation
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ICS9248-135
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable) Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 43 45 46 -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION SEL24_48# (48MHz when set to 0) (24MHz when set to 1) R e s e r ve d R e s e r ve d R e s e r ve d CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact) R e s e r ve d
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 14 13 12 11 9 8 7
PWD 1 1 1 1 1 1 1 1
DESCRIPTION (CPU2.5_3.3#) PCICLK6 (Act/Inact) PCICLK5 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK_F (Act/Inact)
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 32 31 29 28 -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact) R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
BIT PIN# PWD Bit 7 25 1 Bit 6 26 1 Bit 5 41 1 Bit 4 40 1 Bit 3 38 1 Bit 2 37 1 Bit 1 35 1 Bit 0 34 1
DESCRIPTION 24_48MHz 48MHz SDRAM_F1 SDRAM_F0 SDRAM7 SDRAM6 SDRAM5 SDRAM4
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 48 1 Bit 0 2 1
Notes:
DESCRIPTION R e s e r ve d R e s e r ve d FS3# FS2# FS1# FS0# REF1 (Act/Inact) REF0 (Act/Inact)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 0
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Note: Don't write into this register, writing into this register can cause malfunction
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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5
ICS9248-135
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used both to provide the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. When no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, then only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS9248-135
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-135. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-135. 3. All other clocks continue to run undisturbed. (including SDRAM outputs).
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7
ICS9248-135
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK SDRAM PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-135 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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8
ICS9248-135
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-135. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-135 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-135 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248-135. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
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9
ICS9248-135
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-135. All other clocks will continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
Notes: 1. All timing is referenced to the internal CPU clock. 2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to the SDRAM clocks inside the ICS9248-135. 3. All other clocks continue to run undisturbed.
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10
ICS9248-135
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Operating IDD3.3OP66 CL = 0 pF; Select @ 66MHz Supply Current IDD3.3OP100 CL = 0 pF; Select @ 100MHz IDD3.3OP133 CL = 0 pF; Select @ 133MHz Input frequency Fi VDD = 3.3 V; Input Capacitance1 CIN Logic Inputs CINX X1 & X2 pins Transition Time1 Ttrans To 1st crossing of target Freq. 1 Clk Stabilization TSTAB From VDD = 3.3 V to 1% target Freq.
1
MIN 2 VSS-0.3
11 27
MAX UNITS VDD+0.3 V 0.8 V 148 180 mA 150 180 mA 161 mA 14.318 16 MHz 5 pF 36 45 pF 3 ms 3 ms 2.39 4 ns
TYP
tCPU-PCI VT = 1.5 V Skew Guaranteed by design, not 100% tested in production.
1
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz Operating Supply IDD2.5OP100 CL = 0 pF; Select @ 100 MHz Current IDD2.5OP133 CL = 0 pF; Select @ 133 MHz tCPU-SDRAM VT = 1.5 V; VTL = 1.25 V Skew1 VT = 1.5 V; VTL = 1.25 V tCPU-PCI 1
1
TYP 6.13 9.22 11.6 273 2.25
MAX 30
500 4
UNITS mA mA mA ps ns
Guaranteed by design, not 100% tested in production.
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ICS9248-135
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS VO=VDD*(0.5) Output Impedance RDSP2A1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle
1
MIN 10 10 2
TYP 36.5 29 2.85 0.31 -45 29 1.24 1.6 52.6 80.8 128
MAX 40 40 0.4 -19 2 2 62 175 250
UNITS
RDSN2A1 VOH1a VOL1a IOH1a IOL1a tr1a1 tf1a1 dt1a1 tsk1a1 tjcyc-cyc1a1
VO=VDD*(0.5) IOH = -20.0 mA IOL = 12 mA VOH = 2 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V

V V mA mA ns ns % ps ps
22 0.4 0.4 45
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP 1 VO=VDD*(0.5) 10 36.5 Output Impedance RDSP2A Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle
1
MAX UNITS 40 40 0.4 -21 1.6 1.6 55 175 250 350
RDSN2A1 VOH1B VOL1B IOH1B IOL1B tr1B1 tf1B1 dt1a1 tsk1a1 tjcyc-cyc1B1 tjcyc-cyc1B1
VO=VDD*(0.5) IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.25 V CPU, SDRAM Synchronous VT = 1.25 V CPU, SDRAM Asynchronous
10 2
19
45
29 2.3 0.31 -39 26 1.03 1.26 51.7 66.1 170 124.5
V V mA mA ns ns % ps ps ps
Guaranteed by design, not 100% tested in production.
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ICS9248-135
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
MIN 12 12 2.4
TYP 21 21 3.3 0.17 -62 43 1.62 1.81
MAX UNITS 55 55 0.4 -33 2.2 2.2 55 500 350
RDSP1
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -18 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSP1 VOH2 VOL2 IOH2 IOL2 tr2 tf2 dt2 tsk2 tjcyc2

V V mA mA ns ns % ps ps
38
Duty Cycle
45 -350
49.8 200 306
Skew Jitter, Cycle-to-cycle
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle RDSP2A1 RDSN2A1 VOH3 VOL3 IOH3 IOL3 Tr31 Tf31 Dt31 VO=VDD*(0.5) VO=VDD*(0.5) IOH = -25 mA IOL = 20 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V 10 10 2.4 TYP 17 18 2.9 0.32 -73 50 1.14 1.38 51.8 MAX 20 20 0.4 -40 2 2 57 UNITS

V V mA mA ns ns %
41 0.4 0.4 47
Skew1(0-1,2,4,5,7,10,11) Skew (0-6,6,8,9,12,13) Jitter, Cycle-to-cycle
1
Tsk1 Tsk1 tjcyc
VT = 1.5 V VT = 1.5 V VT = 1.5 V
155.5 298.5 369.17
250 500 650
ps ps ps
1
Guarenteed by design, not 100% tested in production.
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ICS9248-135
Electrical Characteristics - 48MHz, REF_0
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time 48MHz Fall Time 48MHz Duty Cycle 48MHz Rise Time1 REF_0 Fall Time1 REF_0 Duty Cycle1 REF_0 Jitter, 48MHz Jitter, REF_0
1 1 1
MIN 12 12 2.4
TYP 21 21 3.3 0.17 -62 57 1.78 1.92
MAX 55 55 0.4 -22 2 2 55 2 2 55 700 1500
UNITS
RDSP1
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -18 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSP1 VOH2 VOL2 IOH2 IOL2 tr2 tf2 dt2 tr2 tf2

V V mA mA ns ns % ns ns % ps ps
16
45
52 1.32 1.56
dt2 tjcyc2 tjcyc2
45 -350
52.2 500.6 1243
Electrical Characteristics - REF_1;24/48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 24_48MHz Fall Time1 24_48MHz Duty Cycle1 24_48MHz Rise Time1 REF_1 Fall Time1 REF_1 Duty Cycle1 REF_1 Jitter, 24_48MHz Jitter, REF_1
1
MIN 20 20 2.4
TYP 42 43 2.6 0.3 -26 22 1.75 1.88
MAX 60 60 0.4 -22 4 4 55 4 4 55 1000 1500
UNITS
RDSP5
1
VO=VDD*(0.5) Output P VO=VDD*(0.5) Output N IOH = -14 mA IOL = 6mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSN51 VOH4 VOL4 IOH4 IOL4 tr4 tf4 dt4 tr4 tf4 dt4 tjcyc4 tjcyc4

V V mA mA ns ns % ns ns % ps ns
16
45
52 2.22 2.43
45 -1
51.1 727 1208
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
14
ICS9248-135
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX 2.794 0.406 0.343 0.254 10.668 7.595 0.635 1.016 8 MIN .095 .008 .008 .005 .395 .291 .015 .020 0 MAX .110 .016 .0135 .010 .420 .299 .025 .040 8 2.413 0.203 0.203 0.127 10.033 7.391 0.381 0.508 0
A A1 b c D E E1 e h L N VARIATIONS N 48
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
SEE VARIATIONS
SEE VARIATIONS
D mm. MIN 15.748 MAX 16.002 MIN .620
D (inch) MAX .630
6/1/00 REV B
JEDEC MO-118 DOC# 10-0034
Ordering Information
ICS9248yF-135-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
15
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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